Dear Colleagues,
Send email to nitincs@gmail.com
We invite references of suitable candidates for critical positions in Noida. We are looking at candidates with high personal values and excellent technical capabilities; people whom you have either worked with previously or know personally or received good feedback.
Req No | Position | Key Technical Skills required | Exp and Qualification | Location |
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1360BR/ 1362BR/ 1363BR | R&D Engineer, Sr. II | Transistor level circuit design, CMOS design fundamentals, SRAM/ROM architecture, sub micron design issues, compiler modules for CMOS SRAM memories, including physical tiling, netlist generation, timing analysis | (7-10 Years of exp); BE/B Tech (EE) or MS/ ME/M Tech(EE/VLSI) | Noida (IN20) |
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1585 – 90BR | R&D Engineer II | Full custom layout design, physical design methodologies/ Physical design phases: Physical Verification, Signal integrity. | (2-5 Years of exp); BE/ B Tech (EE) or MS/ ME/ M Tech (EE/VLSI) | Noida (IN20) |
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1170BR | R&D Engineer, Sr. II | C/C++ programming, Object Oriented Design & Design Patterns, data structures & algorithms, software development processes, Knowledge of compiler technology and processor architectures, LLVM, SystemC, Simulators, processor verification | (10+ Years of exp); BE/ B Tech (CS/EE) or MS/ ME /M Tech (CS/EE/VLSI) | Noida (IN11) |
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1422BR | CAE, Sr. I | Post – sales support, understanding of the design process, ASIC design flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products and productknowledge in any of the areas of Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design | (6+ Years of exp); BE/ B Tech (CS/EE) or MS/ ME/ M Tech (CS/ EE/ VLSI) | Noida (IN20) |
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1464BR | R&D Engineer I | Verilog/VHDL, timing library formats, DFT, Noise Analysis, EM/IR Analysis. Proficient in scripting using Tcl, Shell scripting, perl & C/C++. | (1-4 Years of exp); BE/B Tech (EE) or MS/ ME/ M Tech(EE/VLSI) | Noida (IN20) |
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1356BR/1358BR/1462BR | R&D Engineer II | Transistor level circuit design, CMOS design fundamentals, SRAM/ROM architecture, sub micron design issues, compiler modules for CMOS SRAM memories, including physical tiling, netlist generation, timing analysis | (2-6 Years of exp); BE/ B Tech (EE) or MS/ ME/ M Tech (EE/VLSI) | Noida (IN20) |
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1605BR | CAD Engineer II | developing and supporting EDA tools, generating and maintaining design rule checkers, layout vs. schematic comparison command files, electric rule checkers, generating backend technology data files for each foundry and technology | (2-6 Years of exp); BE/ B Tech (CS/EE) or MS/ ME/ M Tech (CS/EE/VLSI) | Noida (IN20) |
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1508BR/1509BR/1510BR/ 1568BR/ 1569BR | R&D Engineer/ I/ II/ Sr. I | Sound in C/C++, Experience in SoC peripherals modeling using C/C++/SystemC/HDL, Knowledge of TLM, Understanding of Processor/Peripheral model internals/Interconnects | (3+ Years of exp); BE/ B Tech (CS/EE) or MS/ ME/ M Tech (CS/EE/VLSI) | Noida (IN11) |
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